virtio-pci-device summary

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
struct msi_msg {
>---u32>address_lo;>/* low 32 bits of msi message address */
>---u32>address_hi;>/* high 32 bits of msi message address */
>---u32>data;>-->---/* 16 bits of msi message data */
};

struct msi_desc {
>---/* Shared device/bus type independent data */
>---struct list_head>--->---list;
>---unsigned int>--->--->---irq;
>---unsigned int>--->--->---nvec_used;
>---struct device>-->--->---*dev;   // 关联设备
>---struct msi_msg>->--->---msg;
>---struct cpumask>->--->---*affinity;

>---union {
>--->---/* PCI MSI/X specific data */
>--->---struct {
>--->--->---u32 masked;
>--->--->---struct {
>--->--->--->---__u8>---is_msix>>---: 1;
>--->--->--->---__u8>---multiple>---: 3;
>--->--->--->---__u8>---multi_cap>--: 3;
>--->--->--->---__u8>---maskbit>>---: 1;
>--->--->--->---__u8>---is_64>-->---: 1;
>--->--->--->---__u16>--entry_nr;
>--->--->--->---unsigned default_irq;
>--->--->---} msi_attrib;
>--->--->---union {
>--->--->--->---u8>-mask_pos;
>--->--->--->---void __iomem *mask_base;
>--->--->---};
>--->---};

>--->---/*
>--->--- * Non PCI variants add their data structure here. New
>--->--- * entries need to use a named structure. We want
>--->--- * proper name spaces for this. The PCI part is
>--->--- * anonymous for now as it would require an immediate
>--->--- * tree wide cleanup.
>--->--- */
>--->---struct platform_msi_desc platform;
>--->---struct fsl_mc_msi_desc fsl_mc;
>---};
};

/**
 * struct irq_common_data - per irq data shared by all irqchips
 * @state_use_accessors: status information for irq chip functions.
 *>->--->---Use accessor functions to deal with it
 * @node:>-->---node index useful for balancing
 * @handler_data:>--per-IRQ data for the irq_chip methods
 * @affinity:>-->---IRQ affinity on SMP. If this is an IPI
 *>->--->---related irq, then this is the mask of the
 *>->--->---CPUs to which an IPI can be sent.
 * @effective_affinity:>The effective IRQ affinity on SMP as some irq
 *>->--->---chips do not allow multi CPU destinations.
 *>->--->---A subset of @affinity.
 * @msi_desc:>-->---MSI descriptor
 * @ipi_offset:>>---Offset of first IPI target cpu in @affinity. Optional.
 */
struct irq_common_data {
>---unsigned int>--->---__private state_use_accessors;
#ifdef CONFIG_NUMA
>---unsigned int>--->---node;
#endif
>---void>--->--->---*handler_data;
>---struct msi_desc>>---*msi_desc; // msi descriptor
>---cpumask_var_t>-->---affinity;
#ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK
>---cpumask_var_t>-->---effective_affinity;
#endif
#ifdef CONFIG_GENERIC_IRQ_IPI
>---unsigned int>--->---ipi_offset;
#endif
};

/**
 * struct irq_data - per irq chip data passed down to chip functions
 * @mask:>-->---precomputed bitmask for accessing the chip registers
 * @irq:>--->---interrupt number
 * @hwirq:>->---hardware interrupt number, local to the interrupt domain
 * @common:>>---point to data shared by all irqchips
 * @chip:>-->---low level interrupt hardware access
 * @domain:>>---Interrupt translation domain; responsible for mapping
 *>->--->---between hwirq number and linux irq number.
 * @parent_data:>---pointer to parent struct irq_data to support hierarchy
 *>->--->---irq_domain
 * @chip_data:>->---platform-specific per-chip private data for the chip
 *>->--->---methods, to allow shared chip implementations
 */
struct irq_data {
>---u32>>--->---mask;
>---unsigned int>--->---irq;
>---unsigned long>-->---hwirq;
>---struct irq_common_data>-*common;
>---struct irq_chip>>---*chip;
>---struct irq_domain>--*domain;
#ifdef>-CONFIG_IRQ_DOMAIN_HIERARCHY
>---struct irq_data>>---*parent_data;  // 保存父级 
#endif
>---void>--->--->---*chip_data; // chip_data = apic_chip_data
};

struct apic_chip_data {
>---struct irq_cfg>->---hw_irq_cfg;
>---unsigned int>--->---vector;
>---unsigned int>--->---prev_vector;
>---unsigned int>--->---cpu;
>---unsigned int>--->---prev_cpu;
>---unsigned int>--->---irq;
>---struct hlist_node>--clist;
>---unsigned int>--->---move_in_progress>---: 1,
>--->--->--->---is_managed>->---: 1,
>--->--->--->---can_reserve>>---: 1,
>--->--->--->---has_reserved>--->---: 1;
};

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
//如果是arch_setup_msi_irqs
arch_setup_msi_irqs
	-> native_setup_msi_irqs
		-> domain = msi_default_domain = pci_msi_create_irq_domain(fn, &pci_msi_domain_info, parent)
			-> msi_domain_alloc_irqs(domain, &dev->dev, nvec);
				-> (every_entry) __irq_domain_alloc_irqs
					|-> irq_domain_alloc_descs  //分配irq号并初始化所有相关的数据结构
						-> __irq_alloc_descs
							// 其中全局变量allocated_irqs为bitmap，表示irq号是否已经分配
							-> bitmap_find_next_zero_area(allocated_irqs, IRQ_BITMAP_BITS,
							-> alloc_descs
								-> alloc_desc // 初始化irq_desc
								-> irq_insert_desc
								// // 设置bitmap的相应位， 表示已分配
								-> bitmap_set(allocated_irqs, start, cnt) 
					|-> irq_domain_alloc_irqs_hierarchy
						-> domain->ops->alloc(domain, irq_base, nr_irqs, arg);
							->  = x86_vector_alloc_irqs
								-> assign_irq_vector_policy
									-> assign_irq_vector
										-> assign_vector_locked
											// 分配irq对应的vector
											// 设置apic_chip_data中的vector字段
											-> irq_matrix_alloc
											// 更新irq对应的apic_data变量，并设置per_cpu变量
											-> apic_update_vector
											// 更新irq对应的apci_data变量中的irq_cfg变量
											-> apic_update_vector_cfg
                 //设置 desc->irq_common_data.msi_desc
                 // 设置 desc->irq = virq
                 -> (every_entry in desc->nvec_used) irq_set_msi_desc_off(virq, i, msi_desc);
				 -> (for_each_msi_entry) irq_domain_activate_irq
					-> __irq_domain_activate_irq
						-> domain->ops->activate(domain, irqd, reserve)
                        	-> msi_domain_activate
                        		// (构造Message Address和Message Data的流程)
                        		-> irq_chip_compose_msi_msg
                        			// 递归找到最顶级的irq_data
                        			-> pos->chip->irq_compose_msi_msg(pos, msg);
                                        // 设置 Message Address和data的internal函数
                                    	-> irq_msi_compose_msg
                        		// 写配置空间
                        		-> irq_chip_write_msi_msg
                        			-> chip->irq_write_msi_msg(data, msg);
                                    	-> pci_msi_domain_write_msg
                                    		// 将desc中的Message Address和Message Data写到
                                    		// PCI设备的配置空间中
                                    		-> __pci_write_msi_msg 
                                                          
/*
static const struct irq_domain_ops x86_vector_domain_ops = {
>---.alloc>->---= x86_vector_alloc_irqs,
>---.free>-->---= x86_vector_free_irqs,
>---.activate>--= x86_vector_activate,
>---.deactivate>= x86_vector_deactivate,
#ifdef CONFIG_GENERIC_IRQ_DEBUGFS
>---.debug_show>= x86_vector_debug_show,
#endif
};
*/
                                                          
start_kernel
	-> early_irq_init
		-> arch_early_irq_init
			-> irq_set_default_host(x86_vector_domain);
            	-> irq_default_domain = x86_vector_domain_ops
           	-> arch_init_msi_domain(x86_vector_domain);

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
static void irq_msi_compose_msg(struct irq_data *data, struct msi_msg *msg)
{
    // 由irq_data找到irq_cfg
>---struct irq_cfg *cfg = irqd_cfg(data);

>---msg->address_hi = MSI_ADDR_BASE_HI;

>---if (x2apic_enabled())
>--->---msg->address_hi |= MSI_ADDR_EXT_DEST_ID(cfg->dest_apicid);

>---msg->address_lo =
>--->---MSI_ADDR_BASE_LO |
>--->---((apic->irq_dest_mode == 0) ?
>--->--->---MSI_ADDR_DEST_MODE_PHYSICAL :
>--->--->---MSI_ADDR_DEST_MODE_LOGICAL) |
>--->---MSI_ADDR_REDIRECTION_CPU |
>--->---MSI_ADDR_DEST_ID(cfg->dest_apicid);

>---msg->data =
>--->---MSI_DATA_TRIGGER_EDGE |
>--->---MSI_DATA_LEVEL_ASSERT |
>--->---MSI_DATA_DELIVERY_FIXED |
>--->---MSI_DATA_VECTOR(cfg->vector);  ?/ 设置最低8位为vector
}

// arch/x86/include/asm/msidef.h
#define MSI_ADDR_BASE_HI>--->---0
#define MSI_ADDR_BASE_LO>--->---0xfee00000